A Dynamic Congestion Management Method for Reconfigurable Network on Chip

Document Type : Persian Original Article

Authors

1 Computer Engineering Department, Faculty of Engineering, Vali-e-Asr University of Rafsanajn.

2 Computer Engineering Department, Faculty of Engineering, Vali-e-Asr University of Rafsanjan

Abstract

In this paper, an efficient approach for dynamic congestion management and traffic control of reconfigurable network-on-chip (NoC) is proposed. In this approach that called DyCM, the objectives of improving the parameters of delay, area, throughput and power consumption are pursued. Using he proposed scheme in the router control unit, several virtual channels on each port based on the network traffic are supported. Dynamic and non-uniform allocation of virtual channels, as well as management of turning on and off virtual channels, ports and routers, considerably reduce power consumption of the routers, and also result in increasing throughput. The overhead of the proposed design is increasing the router area, due to the complexity of the power management unit. To reduce the area overhead and to increase the speed of the router, we have reduced the number of pipeline stages in the proposed router. The evaluations show that the DyCM offers higher performance in terms of speed, power consumption and network throughput than recent related architectures.

Keywords

References

S. Kundu, S. Chattopadhyay, “Network-on-Chip: The Next Generation of System-on-Chip Integration,” 1st Edition, CRC Press, 2017.
S. Ma, L. Huang, M. Lai, W.Shi, “Networks-on-Chip, From Implementations to Programming Paradigms,” 1st Edition, Morgan Kaufmann, 2014.
A. F. Noghondar, M. Reshadi, N. Bagherzadeh, “Reducing bypass-based network-on-chip latency using priority mechanism,” IET Computers & Digital Techniques, Vol.12, No.1, pp. 1-8, 2018.
C. Li, D. Dong, Z. Lu, X. Liao, “RoB-Router: A Reorder Buffer Enabled Low Latency Network-on-Chip Router,” IEEE Transactions on Parallel and Distributed Systems, Vol.29, No.9, pp. 2090-2104, 2018.
Y. Chang, Y. S. Huang, M. Poremba, V. Narayanan, Y. Xie, C. King, “TS-router: On maximizing the quality-of-allocation in the on-chip network,” In Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture (HPCA’2013), pp. 390–399, 2013.
I. Seitanidis, A. Psarras, K. Chrysanthou, C. Nicopoulos, G. Dimitrakopoulos, “ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip,” IEEE Transactions on VLSI Systems, Vol.23, No.12, pp. 3015-3028, 2015.
A. Psarras, J. Lee, I. Seitanidis, C. Nicopoulos, G. Dimitrakopoulos, “PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels,” IEEE Transactions on Computer Aided Design, Vol.35, No.5, pp. 844-857, 2016.
M. Asadinia, M. Modarressi, H. Sarbazi-Azad, “New Non-contiguous Processor Allocation Algorithm in Mesh-based CMPs Using Virtual Point-to-point Links,” IET Computers and Digital Techniques (IET-CDT), Vol.6, No.5, 2012.
K. Han, J. Lee, J. Lee, W. Lee, M. Pedram, “TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion,” IEEE Transactions on Computer Aided Design, Vol.37, No.2, pp. 458-471, 2018.
H. K. Mondal, S. Deb, “An energy efficient wireless Network-on-Chip using power-gated transceivers,” Proceedings of SOCC, pp. 243-248, 2014.
V. Catania, A. Mineo, S. Monteleone, M. Palesi and D. Patti, “Cycle-Accurate Network on Chip Simulation with Noxim,” ACM Transactions on Modeling and Computer Simulation, Vol.27, No.1, 2016.
V. Soteriou, L. Peh, “Exploring the design space of selfregulating power-aware on/off interconnection networks,” IEEE Transactions on Parallel and Distributed Systems, Vol.18, No.3, 2007.
K.-L. Tsai, H.-T. Chen, Y. Lin, “Power and Area Efficiency NoC Router Design for Application-Specific SoC by Using Buffer Merging and Resource Sharing,” ACM Transactions on Design Automation of Electronic Systems (TODAES) , Vol.19, No.4, Article 36, 2014.
M. Modarressi, H Sarbazi-Azad, “A High-Performance and Low-Power Reconfigurable Network-on-Chip Architecture,” Chapter 13 of Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication, IGI Global Pubs, 2010.
D. Matos, C. Concatto, M. Kreutz, F. Kastensmidt, L. Carro, A. Susin, “Reconfigurable routers for low power and high performance,” IEEE Transaction on VLSI Systems, Vol.19, No.11, pp. 2045-2057, 2011.
M. Kumar, K. Kumar, S. K. Gupta, Y. Kumar. “FPGA Based Design of Area Efficient Router Architecture for Network on Chip (NoC),” International Conference on Computing, Communication and Automation (ICCCA), 2016.
C. Bobda, A. Ahmadinia, M. Majer, J. Teich, S. Fekete, J. van der Veen, “DyNoC: A Dynamic Infrastructure for Communication In Dynamically Reconfigurable Devices,” International Conference on Field Programmable Logic and Applications, pp. 153-158, 2005.
A. Khodwe, V. K. Rajput, C. N. Bhoyar, P. M. Nerkar, “VHDL Implementation Of Reconfigurable Crossbar Switch For Binoc Router,” International Journal Of Scientific & Technology Research, Vol.2, issue 5, 2013.
M. B. Stuart, M. B. Stensgaard, J. Sparso, “The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation,”ACM Transactions on Embedded Computing Systems, Vol.10, No.4, Article 45, 2011.
S. Bayar, “Reconfigurable Network-On-Chip (NoC) Architectures for Embedded Systems,” PhD. Thesis Bogaziçi University, 2015.
R. Tessier, K. Pocek, A. DeHon, “Reconfigurable Computing Architectures,” in Proceedings of the IEEE, Vol.103, No.3, 2015.
T. V. Chu, S. Sato, K. Kise, “Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA,” ACM Transaction on Reconfigurable Technology Systems, Vol.10, No.4, article 27, pp. 1-27, 2017.
J. Lee, C. Nicopoulos, H. Lee, J. Kim, “Centaur: A Hybrid Network-on-Chip Architecture Utilizing Micro-Network Fusion,” Design Automation for Embedded Systems, Vol.18, Issue 3–4, pp. 121–139, 2014.
L. Devaux, S. B. Sassi, S. Pillement, D. Chillet, D. Demigny “Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures,” International Journal of Reconfigurable Computing, Article 6, 2010.
A.F. Noghondar, M. Reshadi, “A low-cost and latency bypass channel-based on-chip network,” Journal of Supercomputing, Vol.71, No.10, pp. 1–17, 2015.
C. Wang, N. Bagherzadeh, “Design and Evaluation of a High Throughput QoS-Aware and Congestion-Aware Router Architecture for Network-on-Chip,” Microprocessors and Microsystems, Vol.38, No.4, pp. 304 – 315, 2014.
V. Y. Raparti, N. Kapadia, S. Pasricha, “ARTEMIS: An Aging-Aware Runtime Application Mapping Framework for 3D NoC-Based Chip Multiprocessors,” IEEE Transactions on Multi-Scale. Computing Systems, Vol.3, No.2, pp. 72-85, 2017.
Z. Ghaderi, A. Alqahtani, N. Bagherzadeh, “AROMa: Aging-Aware Deadlock-Free Adaptive Routing Algorithm and Online Monitoring in 3D NoCs,” IEEE Transactions on Parallel and Distributed Systems, Vol.29, No.4, pp. 772-788, 2018.
E. Chang, H. Hsin, C. Chao, S. Lin, A. Wu, “Regional ACO-Based Cascaded Adaptive Routing for Traffic Balancing in Mesh-Based Network-on-Chip Systems,” IEEE Transactions on Computers, Vol.64, No.3, pp. 868-875, 2015.
I. Perez, E. Vallejo, R. Beivide, “Efficient Router Bypass via Hybrid Flow Control,” 11th International Workshop on Network on Chip Architectures (NoCArc), Fukuoka, pp. 1-6,2018.
N. E. Jerger, T. Krishna, L.-S. Peh, “On-Chip Networks”, Morgan & Claypool Publishers, Second Edition, Vol. 12. 2017.
S. A. R. Jafri, Y. J. Hong, M. Thottethodi, T. N. Vijaykumar, “Adaptive flow control for robust performance and energy,” in MICRO, pp. 433–444, 2010.
A. Psarras, I. Seitanidis, C. Nicopoulos, G. Dimitrakopoulos, “ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing,” in IEEE Transactions on Computers, Vol. 65, No. 10, pp. 3136-3147, 2016.
K. Latif, A. Rahmani, L. Guang, T. Seceleanu and H. Tenhunen, “PVS-NoC: Partial Virtual Channel Sharing NoC Architecture,” 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing, Ayia Napa, pp. 470-477, 2011.
M. Lanzar, R. Bourguiba, J. Mouine, “Buffers Sharing Switch Design Exploiting Dynamic Traffic Orientation in a NoC,” 15th International Multi-Conference on Systems, Signals & Devices (SSD), Hammamet, pp. 1032-1036, 2018.
M. Liu, M. Becker, M. Behnam, T. Nolte, “A dependency-graph based priority assignment algorithm for real-time traffic over NoCs with shared virtual-channels,” IEEE World Conference on Factory Communication Systems (WFCS), Aveiro, pp. 1-8, 2016.
A. Kostrzewa, S. Tobuschat, P. Axer, R. Ernst, "Supervised sharing of virtual channels in Networks -on-Chip," 9th IEEE International Symposium on Industrial Embedded Systems (SIES), Pisa, pp. 133-140, 2014.
G. Miorandi, A. Ghiribaldi, S. M. Nowick, D. Bertozzi, “Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study,” 22nd International Conference on Very Large Scale Integration (VLSI-SoC), Playa del Carmen, 2014.
E. A. Rambo, R. Ernst, "Worst-case communication time analysis of networks-on-chip with shared virtual channels," Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, pp. 537-542, 2015.
A. B. Ahmed, D. Fujiki, H. Matsutani, M. Koibuchi, H. Amano, “AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation,” 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Turin, pp. 1-8, 2018.
M. Debnath, D. Konstantinou, C. Nicopoulos, G. Dimitrakopoulos, W. Lin, J. Lee, “Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling,” 2nd International ACM Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS), New York, USA, pp. 8-1, 2017.
W. Dally, B. Towles, “Principles and Practices of Interconnection Networks,” Morgan Kaufmann, 2004.
A. B. Kahng, B. Li, L.-S. Peh, K. Samadi, “ORION 2.0: A Power-Area Simulator for Interconnection Networks,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.20, No.1, pp. 191-196, 2012.
T. Krishna, C.-H. Owen Chen, W. Kwon, L. Peh, “Smart: Single-Cycle Multihop Traversals over a Shared Network on Chip,” IEEE Micro 34(3), 2014.
P. Lotfi-Kamran, M. Modarressi, H. Sarbazi-Azad, “Near-Ideal Networks-on-Chip for Servers,” International Symposium on High-Performance Computer Architecture (HPCA), 2017.
M. K. Papamichael, J. C. Hoe, “CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs,” ACM/SIGDA international symposium on Field Programmable Gate Arrays (FPGA'12), ACM, New York, NY, USA, 2012.
Journal of Soft Computing and Information Technology
Volume 9, Issue 2 - Serial Number 28
Summer
July 2020
Pages 74-86

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