A. Dixit and A. Wood, “The impact of new technology on soft error rates,” in Proc. IEEE Int. Rel. Phys. Symp. (IRPS), pp. 5B.4.1–5B.4.7, 2011.
 H. Kaul, M. Anders, S. Hsu, A. Agarwal, R. Krishnamurthy, and S. Borkar, “Near threshold voltage (NTV) design: Opportunities andChallenges,” in Proc. 49th Annu. Design Autom. Conf. (DAC), pp. 1153–1158, 2012.
 N. Aggarwal and P. Ranganathan and N. P. Jouppi and J. E. Smith, “Configurable Isolation: Building High Availability Systems withCommodity Multi Core Processors”, 34th Annual InternationalSymposium on Computer Architecture, pp.340–347, 2007.
 E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo, and T. Toba, “Impact of scaling on neutron induced soft error in SRAMs from a 250 nm to a 22 nm design rule,” IEEE Trans. Electron Devices, vol. 57, no. 7, pp. 1527–1538, July, 2010.
 D. Radaelli, H. Puchner, S. Wong, and S. Daniel, “Investigation of multibit upsets in a 150 nm technology SRAM device,” IEEE Trans.Nucl. Sci., vol. 52, no. 6, pp. 2433–2437, Dec. 2005.
 B. Sangchoolie, K. Pattabiraman and J. Karlsson, “One Bit is (Not) Enough: An Empirical Study of the Impact of Single and Multiple Bit Flip Errors”, 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), USA, pp.26–29, 2017.
 H. Cho , S. Mirkhani, C.Y. Cher, J. A. Abraham and S. Mitra, “Quantitative evaluation of soft error injection techniques for robust system design”, in Proceedings of the 50th ACM/EDAC/IEEE Design Automation Conference, pp.1–10, 2013.
 G. A. Kanawati, N. A. Kanawati and J. A. Abraham, “EMAX: An automatic extractor of high level error models”, in Proceedings of the 9th AIAA Computing in Aerospace Conference, pp.1297–1306, 1993.
 J. F. Ziegler et al,"IBM experiments in soft fails in computer electronics (1978–1994)”, IBM Journal of Research and Development, Vol.40, No.1, pp.3–18, 1996.
 A. Chatzidimitriou, G. Papadimitriou, C. Gavanas, G. Katsoridas and D. Gizopoulos, "Multi-Bit Upsets Vulnerability Analysis of Modern Microprocessors," 2019 IEEE International Symposium on Workload Characterization (IISWC), pp. 119-130,,2019.
 Chabot, A., Alouani, I., Nouacer, R. et al. A Memory Reliability Enhancement Technique for Multi Bit Upsets. J Sign Process Syst 93,pp. 439–459 (2021).
 S. A. Asghari, H. Taheri, H.Pedram and O. Kaynak,”Software-Based Control Flow Checking Against Transient Faults in Industrial Environments”,IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, Vol.10,No.1,pp.481–490,2014.
 Q. Lu, G. Li and K. Pattabiraman, M. S. Gupta and .J. A. Rivers ,”Configurable Detection of SDC causing Errors in Programs” , ACM Transactions on Embedded Computing Systems (TECS), Vol.16,2017.
 S. S. Mukherjee, J. Emer and S. K. Reinhardt,”The Soft Error Problem: An Architectural Perspective”, the 11th International Symposium on HighPerformance Computer Architecture (HPCA), USA, 2005.
 A.Rohani, “Modelling and Mitigation of Soft Errors in CMOS Processors”, Ph.D. Thesis ,University of Twente, 2014.
 X. Meng, Q. Tan, Z. Shao, N. Zhang, J. Xu and H. Zhang, “SEInjector: A Dynamic Fault Injection Tool for Soft Errors on X86”, 2017 International Conference on Computer Systems, Electronics and Control (ICCSEC),India,pp.1492–1495,2017.
 X. Meng, Q. Tan, Z. Shao, N. Zhang, J. Xu, H. Zhang,”Optimization Methods for the Fault Injection Tool SEInjector”, 2018 International Conference on Information and Computer Technologies (ICICT), USA, pp.31–35,2018.
 Chun Kai Chang, Sangkug Lym, Nicholas Kelly, Michael B. Sullivan1 and Mattan Erez, “Hamartia: A Fast and Accurate Error Injection Framework”, 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, Luxembourg, pp.101–108, 2018.
 J. Aidemark, J. Vinter, P. Folkesson, J. Karlsson, “GOOFI: generic object–oriented fault injection tool”, International Conference on Dependable Systems and Networks, 2001.
 D. Skarin, R. Barbosa and lohan Karlsson,”GOOFI–2: A Tool for Experimental Dependability Assessment, IEEEIIFIP International Conference on Dependable Systems & Networks DSN,USA, pp557–562,2010.
 F. Ayatolahi, B. Sangchoolie, R. Johansson and J. Karlsson, ”A Study of the Impact of Single Bit–Flip and Double BitFlip Errors on Program Execution”, SAFECOMP, pp.265–276, 2013.
 F.Adamu Fika and Arshad Jhumka, “An Investigation of the Impact of Double Single Bit–Flip Errors on Program Executions”, DEPEND: The Eighth International Conference on Dependability, 2015.
 B. Sangchoolie, F. Ayatolah, R. Johansson; Johan Karlsson,”A Study of the Impact of BitFlip Errors on Programs Compiled with Different Optimization Levels”, Tenth European Dependable Computing Conference, 2014.
 B. Sangchoolie, K. Pattabiraman and J. Karlsson, "An Empirical Study of the Impact of Single and Multiple Bit-Flip Errors in Programs," in IEEE Transactions on Dependable and Secure Computing (TDSC), 2020
 S.A. Asghari and H.Taheri,”An Effective Soft Error Detection Mechanism using Redundant Instructions”, International Arab Journal of Information Technology, Vol.12, No.1, 2015.
 S.A. Asghari, H.R.Zarandi, H.Pedram, M.Ansarinia and M.Khademi, “A Fault Injection Attitude based on Background Debug Mode in Embedded Systems”, Proceedings of the International Conference on Computer Design, DES, USA, 2009.
 S. A. Asghari, A. Abdi, H. Taheri, H. Pedram, S. Pourmozaffari, "SEDSR: Soft Error Detection Using Software Redundancy”, Journal of Software Engineering and Applications, Vol.5, pp.664–670,2012.
 Sh. Feng, Sh. Gupta, A. Ansari and S. Mahlke, "Shoestring: Probabilistic soft error reliability on the cheap", In Proceedings of the Fifteenth Edition of ASPLOS on Architectural Support for Programming Languages and Operating Systems ASPLOS XV,pp.305–336,2010.
 S. K. SastryHari, S. V. Adve, H. Naeimi and P. Ramachandra,Relyzer: Exploiting applicationlevel fault equivalence to analyze application resiliency to transient faults”, In Proceedings of the Seventeenth International Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS XVII ,pp.123–134,2012.
 M. Maghsoudloo, H. R. Zarandi, S. T. Pour Mozafari and N. Khoshavi, “Soft Error Detection Technique in Multi threaded Architectures Using Control Flow Monitoring”, 14th Euromicro Conference on Digital System Design, pp.789–792, 2011.
 M. Maghsoudloo, H.R. Zarandi and N. Khoshavi,”Low Cost Software Implemented Error Detection Technique”, International Symposium on Electronic System Design,pp.318–323,2011.
 J. Vankeirsbilck, N.Penneman, H.Hallez and J.Boydens, “Random Additive Signature Monitoring for Control Flow Error Detection”, TRANSACTIONS ON RELIABILITY, Vol.66, No.4, pp=1178–1192, 2017.
 Q. Lu, G. Li, K.Pattabiraman, M. S. Gupta and .J. A. Rivers,”SDCTune: A model for predicting the SDC proneness of an application for configurable protection”, International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), India2014.
 A. Thomas and K. Pattabiraman, "Error detector placement for soft computation, 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Hungary, 2013.
 N.Narayanamurthy, K. Pattabiraman and M.Ripeanu, “Finding ResilienceFriendly Compiler Optimizations Using Meta–Heuristic Search Techniques”, 12th European Dependable Computing Conference, Sweden, 2016.
 I. Laguna, I. Laguna and D.F. Richards ,”IPAS: Intelligent protection against silent output corruption in scientific applications, IEEE/ACM International Symposium on Code Generation and Optimization (CGO),Spain, 2016.
 N. Seifert et al., “Soft error susceptibilities of 22 nm trigate devices,” IEEE Trans. Nucl. Sci., Vol. 59, No. 6, pp. 2666–2673, Dec. 2012.
 Lu, Q., Li, G., Pattabiraman, K., Gupta, M. S., and Rivers, J. A., (2017), “Configurable Detection of SDC-causing Errors in Programs”, ACM Transactions on Embedded Computing Systems, Vol. 9, No. 4, Article 39, March.
 GU, J., Zheng, W., Zhuang, Y., Zhang, Q., (2019),”Vulnerability analysis of instructions for SDC-causing error detection”, IEEE Access, Volume 7.
 Liu, L., Ci, L., Liu, W., Yang, H., 2019,”Identifying SDC-causing Instructions based on Random forests algorithm”, KSII Transactions on Internet and Information Systems. Vol. 13.
 Yang, N., Wang, Y., (2019),”Identify Silent Data Corruption Vulnerable Instructions Using SVM”, IEEE Access, Volume 7.
 Wang, C., Dryden, N., Cappello, F., Snir, M., (2018), “Neural network based silent error detector”, IEEE International Conference on Cluster Computing (CLUSTER).
[43 ]Thomas, A. and Pattabiraman, K., (2013 ), “Error Detector Placement for Soft Computation”, Dependable Systems and Networks (DSN), 43rd Annual IEEE/IFIP International Conference on, June 2013
 Thati, V.B., Vankeirsbilck, J., Boydens, J., Pissort, D., (2019),”Selective duplication and selective comparison for data flow”, 2019 4th International Conference on System Reliability and Safety (ICSRS).
 Ma, J., Duan, Z., Tang, L., (2019),”Amethodology to assess output vulnerability factors for detecting silent data corruption”, IEEE Access, Volume 7.
 Li, G., Pattabiraman, K., Hari, S.K.S., Sullivan, M., Tsai, T., (2018),”Modeling Soft-error Propagation in programs”, 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN).
 M. Ebrahimi, H. Asadi, and M. B. Tahoori, “A layout–based approach for multiple event transient analysis,” in Proc. 50th Annu. Design Autom. Conf. (DAC), pp. 1–6, 2013.
 N. Khoshavi and A. Samiei, “The Study of Transient Faults Propagation in Multithread Applications”, arXiv, 2016.
 B. Fang, K.Pattabiraman, M.Ripeanu, and S. Gurumurthi, “GPU–Qin A Methodology for Evaluating the Error Resilience of GPGPU Applications”, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), June 2014.
 G.A. Reis, J. Chang, N. Vachharajani, R. Rangan and D.I. August,”SWIFT: software implemented fault tolerance”, International Symposium on Code Generation and Optimization, 2005.
 A. Thomas, K. Pattabirama, “LLFI: An intermediate code level fault injector for soft computing applications”, Workshop on Silicon Errors in Logic System Effects (SELSE), 2013.
 A. Banaiyan Mofrad,M., Ebrahimiy, F., Oborily, M.B., Tahooriy, and N., Dutt, “Protecting Caches Against MultiBit Errors Using Embedded Erasure Coding”, 20th IEEE European Test Symposium (ETS),2015.
 M. Ebrahimi, P. Murali, B. Rao, R.Seyyedi and M. B. Tahoori,"Low–Cost Multiple Bit Upset Correction in SRAMBased FPGA Configuration Frames”.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.24 , No. 3 ,pp.932–943,2016.
 M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austi, T. Mudge and R. B. Brown, “Mibench: A free, commercially representative embedded benchmark suite”, Proceedings of the Fourth Annual IEEE International Workshop on Workload Characterization, pp.3–14,2001.